Apparatus for testing semiconductor integrated circuit and method for testing semiconductor integrated circuit

ABSTRACT

An apparatus for testing a semiconductor integrated circuit includes an input part that inputs circuit description data that describes a circuit structure of the semiconductor integrated circuit, a clock domain of the semiconductor integrated circuit, and a first test vector to be used for testing a normal operation of the semiconductor integrated circuit, and a simulator that performs a simulation on the semiconductor integrated circuit with the use of a test vector. The simulator includes an asynchronous transfer point extraction unit that extracts an asynchronous transfer point in the semiconductor integrated circuit in accordance with the circuit description data and the clock domain that are input through the input part, a simulation unit that calculates a logic circuit output of the semiconductor integrated circuit by performing a simulation in accordance with the circuit description data and the first test vector that are input through the input part, and a second test vector generation unit that generates a second test vector by changing a signal of an asynchronous transfer point of the logic circuit output calculated by the simulation unit in accordance with the asynchronous transfer point extracted by the asynchronous transfer point extraction unit.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2007-223641, filed on Aug. 30,2007; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an apparatus for testing asemiconductor integrated circuit and a method for testing thesemiconductor integrated circuit, and more particularly, to an apparatusfor testing a semiconductor integrated circuit that includes a pluralityof semiconductor elements operating in an asynchronous manner, and amethod for testing the semiconductor integrated circuit.

2. Related Art

Testing a semiconductor integrated circuit that includes resistersasynchronously operating with clocks of different frequencies andinvolves data transfers between a plurality of semiconductor elements iscarried out by performing a simulation with the use of test vectors thatare created by an engineer. Japanese Patent Application Laid-OpenPublication No. 2005-182093 discloses one of those conventional testingmethods.

In recent years, however, the number of clocks has increased in SoCdesigns, and the designs have become complicated. Therefore, the numberof points at which asynchronous transfers occur (hereinafter referred toas the “asynchronous transfer points”) has increased, and the number ofsubject points and items to be tested has also increased. As a result, alarge amount of work time is imposed on each engineer to create testvectors.

In testing a semiconductor integrated circuit that has transfer errorssuch as asynchronous transfers, it is necessary to carry out a test on aviolation equivalent to a transfer error due to metastability, as wellas a test on a simple normal operation.

To reproduce such a violation with test vectors, it is necessary toaccurately grasp the timing in the semiconductor integrated circuit, andconsider various combinations of clock timings provided in the testvectors and transfer data. As a result, the work time imposed on eachengineer to create test vectors has been increasing.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is providedthat an apparatus for testing a semiconductor integrated circuit,comprising:

an input part that inputs circuit description data that describes acircuit structure of the semiconductor integrated circuit, a clockdomain of the semiconductor integrated circuit, and a first test vectorto be used for testing a normal operation of the semiconductorintegrated circuit; and

a simulator that performs a simulation on the semiconductor integratedcircuit with the use of a test vector;

wherein, the simulator including an asynchronous transfer pointextraction unit that extracts an asynchronous transfer point in thesemiconductor integrated circuit in accordance with the circuitdescription data and the clock domain that are input through the inputpart;

a simulation unit that calculates a logic circuit output of thesemiconductor integrated circuit by performing a simulation inaccordance with the circuit description data and the first test vectorthat are input through the input part; and

a second test vector generation unit that generates a second test vectorby changing a signal of an asynchronous transfer point of the logiccircuit output calculated by the simulation unit in accordance with theasynchronous transfer point extracted by the asynchronous transfer pointextraction unit.

According to a second aspect of the present invention, there is providedthat a method for testing a semiconductor integrated circuit,comprising:

inputting circuit description data that describes a circuit structure ofthe semiconductor integrated circuit, a clock domain of thesemiconductor integrated circuit, and a first test vector to be used fortesting a normal operation of the semiconductor integrated circuit;

extracting an asynchronous transfer point of the semiconductorintegrated circuit, in accordance with the circuit description data andclock domain;

calculating a logic circuit output of the semiconductor integratedcircuit by performing a simulation in accordance with the input circuitdescription data and first test vector; and

generating a second test vector by changing a signal of an asynchronoustransfer point of the logic circuit output calculated by the simulationunit in accordance with the extracted asynchronous transfer point.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the structure of a testing apparatusin accordance with the first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example structure of thesemiconductor integrated circuit described in the HDL data 111 inaccordance with the first embodiment of the present invention.

FIG. 3 is a flowchart showing the operation procedures to be carried outby the simulator 120 in a testing process in accordance with the firstembodiment of the present invention.

FIG. 4 is a flowchart showing the operation procedures to be carried outby the asynchronous transfer point extraction unit 121 in theasynchronous transfer point extraction process in accordance with thefirst embodiment of the present invention.

FIG. 5 is a table showing the asynchronous transfer point data 142 inaccordance with the first embodiment of the present invention.

FIG. 6 is a flowchart showing the operation procedures to be carried outby the simulation unit 122 in the first simulation in accordance withthe first embodiment of the present invention.

FIG. 7 is a table showing the logic circuit output data 143 and thefirst external output data 144 in accordance with the first embodimentof the present invention.

FIG. 8 is a flowchart showing the operation procedures to be performedby the second test vector generation unit 123 in the second test vectorgeneration process in accordance with the first embodiment of thepresent invention.

FIG. 9 is a table showing the change data 146 in accordance with thefirst embodiment of the present invention.

FIG. 10 is a flowchart showing the operation procedures to be carriedout by the simulation unit 122 in the second simulation in accordancewith the first embodiment of the present invention.

FIG. 11 is a table showing the logic circuit output data 243 inaccordance with the first embodiment of the present invention.

FIG. 12 is a flowchart showing the operation procedures to be carriedout by a second test vector generation unit 223 in a second test vectorgeneration process in accordance with the second embodiment of thepresent invention.

FIG. 13 is a table showing the logic circuit output and the change data246 in accordance with the second embodiment of the present invention.

FIG. 14 is a table showing the logic circuit output data 343 inaccordance with the third embodiment of the present invention.

FIG. 15 is a flowchart showing the operation procedures to be carriedout by a second test vector generation unit 323 in a second test vectorgeneration process in accordance with the third embodiment of thepresent invention.

FIG. 16 is a table showing the logic circuit outputs and change data 346in accordance with the third embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The following is a description of embodiments of the present invention,with reference to the accompanying drawings. It should be noted that thefollowing embodiments are merely examples and do not limit the scope ofthe present invention.

First Embodiment

First, a first embodiment of the present invention is described.

FIG. 1 is a block diagram showing the structure of a testing apparatusin accordance with the first embodiment of the present invention.

The testing apparatus in accordance with the first embodiment of thepresent invention includes an input part 110, a simulator 120, an outputpart 130, and a memory 140.

The input part 110 inputs a circuit description data (for example,hardware description language data written in Verilog language atregister transfer level, and hereinafter referred to as the “HDL data”)111 that indicates the semiconductor integrated circuit to be tested,clock domain data 112 that indicates the terminal name (hereinafterreferred to as the “clock domain”) of an external clock terminal thatsupplies an operation clock to a flip-flop of the semiconductorintegrated circuit described in the HDL data 111, and a first testvector 113 to be used in a simulation (hereinafter referred to as the“first simulation”) of an operation (hereinafter referred to as the“normal operation”) to be performed in a case where the FF of thesemiconductor integrated circuit described in the HDL data 111 performsa synchronous transfer. For example, the input part 110 is a keyboard ora mouse. The HDL data 111, the clock domain data 112, and the first testvector 113 are input by a user through the input part 110.

The clock domain data 112 may indicate the same clock domain withrespect to more than one external clock terminal.

The simulator 120 runs a control program 141 stored in the memory 140,so as to realize an asynchronous transfer point extraction unit 121, asimulation unit 122, and a second test vector generation unit 123.

The asynchronous transfer point extraction unit 121 carries out anasynchronous transfer point extraction process. In the asynchronoustransfer point extraction process, the asynchronous transfer pointextraction unit 121 refers to the HDL data 111 and the clock domain data112, so as to extract the interelement connection between elements inthe semiconductor integrated circuit that perform asynchronous transfersto each other (the interelement connection will be hereinafter referredto as the “asynchronous transfer point”). The asynchronous transferpoint extraction unit 121 then generates asynchronous transfer pointdata 142, and writes the asynchronous transfer point data 142 into thememory 140.

The simulation unit 122 performs the first simulation. In the firstsimulation, the simulation unit 122 calculates a logic circuit outputand a first external output of the semiconductor integrated circuit byperforming a simulation on the semiconductor integrated circuitdescribed in the HDL data 111 with the use of the first test vector 113.The simulation unit 122 then generates logic circuit output data 143 andfirst external output data 144, and writes the logic circuit output data143 and the first external output data 144 into the memory 140. Thesimulation unit 122 transmits the simulation results to the output part130.

The simulation unit 122 also performs a second simulation. In the secondsimulation, the simulation unit 122 calculates a second external outputof the semiconductor integrated circuit by performing a simulation onthe semiconductor integrated circuit described in the HDL data 111 withthe use of a second test vector 145. The simulation unit 122 thentransmits the simulation result to the output part 130.

The second test vector generation unit 123 carries out a test vectorgeneration process. In the test vector generation process, the secondtest vector generation unit 123 generates the second test vector 145 andchange data 146 in accordance with the asynchronous transfer point data142 and the logic circuit output data 143, and writes the second testvector 145 and the change data 146 into the memory 140. The change data146 includes the name of a signal having the asynchronous transfer pointinserted thereinto, the simulation time, and the contents of the change.

The output part 130 is a display that displays the data that istransmitted from the simulator 120.

The memory 140 stores the control program 141, the asynchronous transferpoint data 142, the logic circuit output data 143, the first externaloutput data 144, the second test vector 145, and the change data 146.

FIG. 2 is a circuit diagram showing an example structure of thesemiconductor integrated circuit described in the HDL data 111 inaccordance with the first embodiment of the present invention.

The HDL data 111 in accordance with the first embodiment of the presentinvention includes an input terminal IN, an output terminal OUT, a firstexternal clock terminal CLKT1, a second external clock terminal CLKT2,and flip-flops FFA to FFD.

The D-terminal of the flip-flop FFA is connected to the input terminalIN, and the Q-terminal of the flip-flop FFA is connected to theD-terminals of the flip-flops FFB and FFC. The flip-flop FFA transfersan output signal sig_A when a first clock CLK1 is supplied as anoperation clock from the first external clock terminal CLKT1.

The D-terminal of the flip-flop FFB is connected to the Q-terminal ofthe flip-flop FFA, and the Q-terminal of the flip-flop FFB is connectedto the D-terminal of the flip-flop FFE. The flip-flop FFB transfers anoutput signal sig_B when the first clock CLK1 is supplied as anoperation clock from the first external clock terminal CLKT1.

The D-terminal of the flip-flop FFC is connected to the Q-terminal ofthe flip-flop FFA, and the Q-terminal of the flip-flop FFC is connectedto the D-terminal of the flip-flop FFD. The flip-flop FFC transfers anoutput signal sig_C when a second clock CLK2 is supplied as an operationclock from the second external clock terminal CLKT2.

The D-terminal of the flip-flop FFD is connected to the Q-terminal ofthe flip-flop FFC, and the Q-terminal of the flip-flop FFD is connectedto the output terminal OUT. The flip-flop FFD transfers an output signalsig_D when the second clock CLK2 is supplied as an operation clock fromthe second external clock terminal CLKT2.

The D-terminal of the flip-flop FFE is connected to the Q-terminal ofthe flip-flop FFB, and the Q-terminal of the flip-flop FFE is connectedto a semiconductor element (not shown). The flip-flop FFE transfers anoutput signal sig_E when the second clock CLK2 is supplied as anoperation clock from the second external clock terminal CLKT2.

In the semiconductor integrated circuit shown in FIG. 2, the signal thatis transmitted from the input terminal IN to the D-terminal of theflip-flop FFA is a logic circuit input, and the output signal sig_Dtransferred from the flip-flop FFD to the output terminal OUT is a logiccircuit output.

FIG. 3 is a flowchart showing the operation procedures to be carried outby the simulator 120 in a testing process in accordance with the firstembodiment of the present invention.

The testing process in accordance with the first embodiment of thepresent invention includes the asynchronous transfer point extractionprocess (S301) to be carried out by the asynchronous transfer pointextraction unit 121, the first simulation (S302) to be performed by thesimulation unit 122, the second test vector generation process (S303) tobe carried out by the second test vector generation unit 123, and thesecond simulation (S304) to be performed by the simulation unit 122.Those processes are carried out in that order.

FIG. 4 is a flowchart showing the operation procedures to be carried outby the asynchronous transfer point extraction unit 121 in theasynchronous transfer point extraction process in accordance with thefirst embodiment of the present invention.

First, the asynchronous transfer point extraction unit 121 refers to theHDL data 111 and the clock domain data 112 that are input through theinput part 110 (S401).

The asynchronous transfer point extraction unit 121 then traces back toan external clock terminal from the clock terminal of each flip-flop ofthe semiconductor integrated circuit described in the HDL data 111 thatis referred to in step S401, and adds the clock domain described in theclock domain data 112 to the external clock terminal tracked as an endterminal (S402). In the example structure shown in FIG. 2, CLKT1 isadded as the clock domain to each clock terminal of the flip-flops FFAand FFB, and CLKT2 is added as the clock domain to each clock terminalof the flip-flops FFC to FFE. As a result, the clock CLK1 is identifiedas the operation clock for the flip-flops FFA and FFB, and the clockCLK2 is identified as the operation clock for the flip-flops FFC to FFE.

The asynchronous transfer point extraction unit 121 then identifies anasynchronous transfer point to be an interelement connection formed by apair of flip-flops having different clock domains added thereto in stepS402, among the interelement connections in the semiconductor integratedcircuit described in the HDL data 111 that is referred to in step S401(S403). In the example structure shown in FIG. 2, the interelementconnection formed by the pair of flip-flops FFA and FFC and theinterelement connection formed by the pair of flip-flops FFB and FFE areidentified as asynchronous transfer points.

The asynchronous transfer point extraction unit 121 then identifiesoutput signals of the asynchronous transfer points identified in stepS403 (S404). In the example structure shown in FIG. 2, the output signalsig_C transferred from the Q-terminal of the flop-flop FFC to theD-terminal of the flip-flop FFD, and the output signal sig_E transferredfrom the Q-terminal of the flip-flop FFE to the semiconductor element(not shown) are identified as the output signals that might becomeerrors in a violation due to metastability.

The procedure of step S404 is repeated until the output signals of allthe asynchronous transfer points identified in step S403 are identified(S405-NO).

If the output signals of all the asynchronous transfer points identifiedin step S403 are identified (S405-YES), the asynchronous transfer pointextraction unit 121 writes the asynchronous transfer points identifiedin step S403 and the output signals identified in step S404 as theasynchronous transfer point data 142 into the memory 140 (S406). In theexample structure shown in FIG. 2, the asynchronous transfer point data142 shown in FIG. 5 is written into the memory 140.

After the procedure of step S406 is carried out, the asynchronoustransfer point extraction process in accordance with the firstembodiment of the present invention is completed.

FIG. 6 is a flowchart showing the operation procedures to be carried outby the simulation unit 122 in the first simulation in accordance withthe first embodiment of the present invention.

First, the simulation unit 122 refers to the HDL data 111 and the firsttest vector 113 that are input through the input part 110 (S601).

The simulation unit 122 then performs a simulation of a normal operationof the semiconductor integrated circuit described in the HDL data 111with the use of the first test vector 113 that is referred to in stepS601 (S602). In step S602, the simulation unit 122 uses a Value ChangeDump function.

The simulation unit 122 then calculates the logic circuit output foreach flop-flop in a normal operation of the semiconductor integratedcircuit described in the HDL data 111 that is referred to in step S601(S603). In the example structure shown in FIG. 2, the values of theoutput signals sig_A to sig_E of the flop-flops FFA to FFE arecalculated as the logic circuit outputs.

The simulation unit 122 then identifies the first external output to bethe logic circuit output transferred to an external output terminalamong the logic circuit outputs calculated in step S603 (S604). In theexample structure shown in FIG. 2, the value of the output signal sig_Cof the flip-flop FFC is identified as the first external output.

The simulation unit 122 then writes the logic circuit outputs identifiedin step S603 as the logic circuit output data 143 into the memory 140,and writes the first external output identified in step S604 as thefirst external output data 144 into the memory 140 (S605). In theexample structure shown in FIG. 2, the logic circuit output data 143 andthe first external output data 144 shown in FIG. 7 are written into thememory 140.

After the procedure of step S605 is carried out, the first simulation inaccordance with the first embodiment of the present invention iscompleted.

FIG. 8 is a flowchart showing the operation procedures to be performedby the second test vector generation unit 123 in the second test vectorgeneration process in accordance with the first embodiment of thepresent invention.

First, the second test vector generation unit 123 refers to theasynchronous transfer point data 142 and the logic circuit output data143 stored in the memory 140 (S801).

The second test vector generation unit 123 then traces the state of thesignal of the asynchronous transfer point in the logic circuit outputdata 143 that is referred to in step S801, identifies the change pointof the signal, and inverts the signal at the change point, so as tomodify the logic circuit outputs (S802). In the example shown in FIG. 7,the signals sig_C (t5) and sig_E (t6) are the signals at the changepoints, so each of those signals is inverted from “1” to “0”. As aresult, the logic circuit outputs shown in FIG. 9 are generated. In theexample shown in FIG. 9, the signals sig_C (t5) and sig_E (t6) cannot bechanged, or data cannot be transferred correctly at t5 and t6.

The procedure of step S802 is repeated until all the change points aresubjected to this procedure (S803-YES). After all the change points aresubjected to the procedure of step S802 (S803-NO), the procedures ofS801 to S803 are repeated for all the asynchronous transfer points(S804-YES). After carrying out the procedures of steps S801 to S803 forall the asynchronous transfer points (S804-NO), the second test vectorgeneration unit 123 writes the logic circuit outputs shown in FIG. 9 asthe second test vector 145 into the memory 140 (S805).

The second test vector generation unit 123 then generates the changedata 146 as shown in FIG. 9, and writes the change data 146 into thememory 140 (S806).

After the procedure of step S806 is carried out, the second test vectorgeneration process in accordance with the first embodiment of thepresent invention is completed.

FIG. 10 is a flowchart showing the operation procedures to be carriedout by the simulation unit 122 in the second simulation in accordancewith the first embodiment of the present invention.

First, the simulation unit 122 refers to the HDL data 111 input throughthe input part 110, and the second test vector 145 and the change data146 stored in the memory 140 (S1001).

The simulation unit 122 then performs a simulation of a violation of thesemiconductor integrated circuit described in the HDL data 111 at thesimulation time according to the change data 146, with the use of thesecond test vector 145 that is referred to in step S1001 (S1002). In theexample structure shown in FIG. 2, a simulation of the signal sig_C isstarted at the simulation time t5 in the change data 146 shown in FIG.9, and a simulation of the signal sig_E is started at the simulationtime t6.

The simulation unit 122 then calculates an external output (hereinafterreferred to as the “second external output”) in the violation of thesemiconductor integrated circuit described in the HDL data 111 that isreferred to in step S1001 (S1003). In the example structure shown inFIG. 2, the value of the output signal sig_C of the flip-flop FFCobtained when the second test vector 145 shown in FIG. 9 is used iscalculated as the second external output.

The simulation unit 122 then refers to the first external output data144 stored in the memory 140, and compares the first external outputswith the second external outputs (S1004).

If the first external outputs and the second external outputs are thesame (S1005-YES), the semiconductor integrated circuit described in theHDL data 111 that is referred to in step S1001 is determined to functionproperly even in a violation (S1006).

If the first external outputs are not the same as the second externaloutputs (S1005-NO), the semiconductor integrated circuit described inthe HDL data 111 that is referred to in step S1001 is determined tofunction abnormally in a violation (S1007). The simulation unit 122 thentransmits the change data 146 stored in the memory 140 to the outputpart 130 (S1008).

After carrying out the procedure of step S1006 or S1007 and theprocedure of step S1008, the simulation unit 122 transmits thedetermination result of step S1006 or S1007 as the simulation result tothe output part 130 (S1009).

After the procedure of step S1009 is carried out, the second simulationin accordance with the first embodiment of the present invention iscompleted.

In accordance with the first embodiment of the present invention, theasynchronous transfer point data 142 is generated, and the second testvector 145 for testing a violation is generated in accordance with theasynchronous transfer point data 142. Accordingly, it is possible toshorten the work time to be imposed on the engineer to create the testvectors for testing a violation of a semiconductor integrated circuithaving asynchronous transfer points.

Also, in the first embodiment of the present invention, the secondsimulation is started at the simulation time of the change data 146.Accordingly, the operation time required for the second simulation canbe shortened.

Also, in the first embodiment of the present invention, the change data146 generated together with the second test vector 145 is output to theoutput part 130. Accordingly, when a semiconductor integrated circuithas a violation, specific information about the violation can beprovided to the engineer.

Second Embodiment

Next, a second embodiment of the present invention is described. Whilethe first embodiment of the present invention is a structure thatgenerates a second test vector for each asynchronous transfer point, thesecond embodiment of the present invention is a structure that generatessecond test vectors for a plurality of asynchronous transfer points atthe same time. Explanation of the aspects of the second embodiment ofthe present invention that are the same as those of the first embodimentof the present invention is not repeated here.

The testing apparatus in accordance with the second embodiment of thepresent invention includes an input part 210, a simulator 220, an outputpart 230, and a memory 240. Those components are the same as those ofthe first embodiment of the present invention.

In the second embodiment of the present invention, the logic circuitoutput data 243 shown in FIG. 11 is stored in the memory 240.

FIG. 12 is a flowchart showing the operation procedures to be carriedout by a second test vector generation unit 223 in a second test vectorgeneration process in accordance with the second embodiment of thepresent invention.

First, the second test vector generation unit 223 refers to asynchronoustransfer point data 242 and the logic circuit output data 243 stored inthe memory 240 (S1201).

The second test vector generation unit 223 then traces the state of thesignal of the asynchronous transfer point of the logic circuit outputdata 243 that is referred to in step S1201, and identifies the changepoint of the signal. If a change point of a signal of anotherasynchronous transfer point exists at the same simulation time as thechange point of the above signal (S1202-YES), the second test vectorgeneration unit 223 inverts the change points of the signals of all theasynchronous transfer points, so as to modify the logic circuit outputs(S1203). In the example shown in FIG. 11, the signals sig_C (t5) andsig_E (t5) are the signals at the change point, so those signals aresimultaneously inverted from “1” to “0”. As a result, the logic circuitoutputs shown in FIG. 13 are generated. In the example shown in FIG. 13,the signals sig_C (t5) and sig_E (t5) cannot be changed, or data cannotbe transferred correctly at t5.

If a change point of a signal of another asynchronous transfer pointdoes not exist at the same simulation time as the change point of theabove signal (S1202-NO), the second test vector generation unit 223inverts only the change point of the signal of the asynchronous transferpoint of the logic circuit output data 243 that is referred to in stepS1201, so as to modify the logic circuit outputs in the same manner asin the first embodiment of the present invention (S1204). In the exampleshown in FIG. 11, the signal sig_C (t7) is the signal at the changepoint, so the signal is inverted from “0” to “1”. As a result, the logiccircuit outputs shown in FIG. 13 are generated. In the example shown inFIG. 13, the signal sig_C (t7) cannot be changed, or data cannot betransferred correctly at t7.

The procedures of steps S1202 to S1204 are repeated until all the changepoints are subjected to those procedures (S1205-YES). After all thechange points are subjected to the procedures of steps S1202 to S1204(S1205-NO), the second test vector generation unit 223 writes the logiccircuit outputs shown in FIG. 13 as the second test vectors 245 into thememory 240 (S1206).

The second test vector generation unit 223 then generates the changedata 246 shown in FIG. 13, and writes the change data 246 into thememory 240 (S1207).

After the procedure of step S1207 is carried out, the second test vectorgeneration process in accordance with the second embodiment of thepresent invention is completed.

In accordance with the second embodiment of the present invention, ifthe change points of signals of a plurality of asynchronous transferpoints exist within the same simulation time, the signals at all thechange points are inverted at the same time. Accordingly, even if a morecomplicated operation than in the first embodiment of the presentinvention is performed to generate test vectors, the work time to beimposed on the engineer can be shortened.

Third Embodiment

Next, a third embodiment of the present invention is described. Whilethe first embodiment of the present invention is a structure thatgenerates a second test vector if a change point at which the signal ofan asynchronous transfer point varies exists within a predeterminedsimulation time, the third embodiment of the present invention is astructure that generates a second test vector if a change point does notexist within the predetermined simulation time. Explanation of theaspects of the third embodiment that are the same as those of the firstand second embodiments of the present invention is not repeated here.

The testing apparatus in accordance with the third embodiment of thepresent invention includes an input part 310, a simulator 320, an outputpart 330, and a memory 340. Those components are the same as those ofthe first embodiment of the present invention.

In the third embodiment of the present invention, the logic circuitoutput data 343 shown in FIG. 14 is stored in the memory 340.

FIG. 15 is a flowchart showing the operation procedures to be carriedout by a second test vector generation unit 323 in a second test vectorgeneration process in accordance with the third embodiment of thepresent invention.

First, the second test vector generation unit 323 refers to asynchronoustransfer point data 342 and the logic circuit output data 343 stored inthe memory 340 (S1501).

The second test vector generation unit 323 then traces the state of thesignal of the asynchronous transfer point of the logic circuit outputdata 343 that is referred to in step S1501. When a change point of asignal is identified (S1502-YES), the second test vector generation unit323 inverts the change point of the signal of the asynchronous transferpoint of the logic circuit output data 343 that is referred to in stepS1501, so as to modify the logic circuit outputs in the same manner asin the first embodiment of the present invention (S1503). In the exampleshown in FIG. 14, the signal sig_E (t6) is the signal at the changepoint, so the second test vector generation unit 323 inverts the signalfrom “1” to “0”. As a result, the logic circuit outputs shown in FIG. 16are generated. In the example shown in FIG. 16, the signal sig_E (t6)cannot be changed, or data cannot be transferred correctly at t6.

If a change point of a signal is not identified (S1502-NO), the secondtest vector generation unit 323 randomly selects any simulation time,and inverts the signals at the asynchronous transfer points existingwithin the selected simulation time, so as to modify the logic circuitoutputs (S1504). In the example shown in FIG. 14, the signal sig_C(t5-t6) is inverted from “1” to “0”, as the signal sig_C does not have achange point. As a result, the logic circuit outputs shown in FIG. 16are generated. In the example shown in FIG. 16, the signal sig_C (t5 tot6) is changed, or data cannot be transferred correctly between t5 andt6.

The procedures of steps S1502 to S1504 are repeated until all the changepoints are subjected to those procedures (S1505-YES). After all thechange points are subjected to the procedures of steps S1502 to S1504(S1505-NO), the procedures of steps S1501 to S1505 are repeated for allthe asynchronous transfer points (S1506-YES). After the procedures ofsteps S1501 to S1505 are carried out for all the asynchronous transferpoints (S1506-NO), the second test vector generation unit 323 writes thelogic circuit outputs shown in FIG. 16 as the second test vector 345into the memory 340 (S1507).

The second test vector generation unit 323 then generates the changedata 346 shown in FIG. 16, and writes the change data 346 into thememory 340 (S1508).

After the procedure of step S1508 is carried out, the second test vectorgeneration process in accordance with the third embodiment of thepresent invention is completed.

In accordance with the third embodiment of the present invention, asignal of an asynchronous transfer point at which there is not a signalchange point can be forcibly changed. Accordingly, even if the qualityof the first test vector is low, it is possible to generate ahigh-quality second test vector.

1. An apparatus for testing a semiconductor integrated circuit,comprising: an input part that inputs circuit description data thatdescribes a circuit structure of the semiconductor integrated circuit, aclock domain of the semiconductor integrated circuit, and a first testvector to be used for testing a normal operation of the semiconductorintegrated circuit; and a simulator that performs a simulation on thesemiconductor integrated circuit with the use of a test vector; wherein,the simulator including an asynchronous transfer point extraction unitthat extracts an asynchronous transfer point in the semiconductorintegrated circuit in accordance with the circuit description data andthe clock domain that are input through the input part; a simulationunit that calculates a logic circuit output of the semiconductorintegrated circuit by performing a simulation in accordance with thecircuit description data and the first test vector that are inputthrough the input part; and a second test vector generation unit thatgenerates a second test vector by changing a signal of an asynchronoustransfer point of the logic circuit output calculated by the simulationunit in accordance with the asynchronous transfer point extracted by theasynchronous transfer point extraction unit.
 2. The apparatus accordingto claim 1, wherein the second test vector generation unit generates thesecond test vector by inverting a signal at a change point at which thesignal of the asynchronous transfer point extracted by the asynchronoustransfer point extraction unit varies, the signal being of the logiccircuit output calculated by the simulation unit.
 3. The apparatusaccording to claim 1, wherein: the asynchronous transfer pointextraction unit extracts a plurality of asynchronous transfer points ofthe semiconductor integrated circuit; and the second test vectorgeneration unit generates the second test vector by simultaneouslyinverting signals at change points at which the signals of the pluralityof asynchronous transfer points extracted by the asynchronous transferpoint extraction unit vary, the signals being of the logic circuitoutput calculated by the simulation unit.
 4. The apparatus according toclaim 1, wherein the second test vector generation unit generates thesecond test vector by inverting the signal of the asynchronous transferpoint of the logic circuit output, when the signal of the asynchronoustransfer point extracted by the asynchronous transfer point extractionunit is a constant signal, the signal being of the logic circuit outputcalculated by the simulation unit.
 5. The apparatus according to claim1, wherein the asynchronous transfer point extraction unit adds theclock domain to a semiconductor element of the semiconductor integratedcircuit, and extracts an interelement connection formed by a pair ofsemiconductor elements to which different clock domains from each otherare added, the interelement connection being extracted as theasynchronous transfer point.
 6. The apparatus according to claim 5,wherein the second test vector generation unit generates the second testvector by inverting the signal at the change point at which the signalof the asynchronous transfer point extracted by the asynchronoustransfer point extraction unit varies, the signal being of the logiccircuit output calculated by the simulation unit.
 7. The apparatusaccording to claim 5, wherein: the asynchronous transfer pointextraction unit extracts a plurality of asynchronous transfer points ofthe semiconductor integrated circuit; and the second test vectorgeneration unit generates the second test vector by simultaneouslyinverting signals at change points at which the signals of the pluralityof asynchronous transfer points extracted by the asynchronous transferpoint extraction unit vary, the signals of the logic circuit outputcalculated by the simulation unit.
 8. The apparatus according to claim5, wherein the second test vector generation unit generates the secondtest vector by inverting the signal of the asynchronous transfer pointof the logic circuit output, when the signal of the asynchronoustransfer point extracted by the asynchronous transfer point extractionunit is a constant signal, the signal being of the logic circuit outputcalculated by the simulation unit.
 9. A method for testing asemiconductor integrated circuit, comprising: inputting circuitdescription data that describes a circuit structure of the semiconductorintegrated circuit, a clock domain of the semiconductor integratedcircuit, and a first test vector to be used for testing a normaloperation of the semiconductor integrated circuit; extracting anasynchronous transfer point of the semiconductor integrated circuit, inaccordance with the circuit description data and clock domain;calculating a logic circuit output of the semiconductor integratedcircuit by performing a simulation in accordance with the input circuitdescription data and first test vector; and generating a second testvector by changing a signal of an asynchronous transfer point of thelogic circuit output calculated by the simulation unit in accordancewith the extracted asynchronous transfer point.
 10. The method accordingto claim 9, wherein the generating a second test vector includesgenerating the second test vector by inverting the signal at the changepoint at which the signal of the extracted asynchronous transfer pointof the calculated logic circuit output varies.
 11. The method accordingto claim 9, wherein: the extracting an asynchronous transfer pointincludes extracting a plurality of asynchronous transfer points of thesemiconductor integrated circuit; and the generating a second testvector includes generating the second test vector by simultaneouslyinverting the signals at the change points at which the signals of theplurality of extracted asynchronous transfer points of the calculatedlogic circuit output vary.
 12. The method according to claim 9, whereinthe generating a second test vector includes generating the second testvector by inverting the signal of the asynchronous transfer point of thelogic circuit output, when the signal of the extracted asynchronoustransfer point of the calculated logic circuit output is a constantsignal.
 13. The method according to claim 9, wherein the extracting anasynchronous transfer point includes adding the clock domain to asemiconductor element of the semiconductor integrated circuit, andextracting an interelement connection formed by a pair of semiconductorelements to which different clock domains from each other are added, theinterelement connection being extracted as the asynchronous transferpoint.
 14. The method according to claim 13, wherein the generating asecond test vector includes generating the second test vector byinverting the signal at the change point at which the signal of theextracted asynchronous transfer point of the calculated logic circuitoutput varies.
 15. The method according to claim 13, wherein: theextracting an asynchronous transfer point includes extracting aplurality of asynchronous transfer points of the semiconductorintegrated circuit; and the generating a second test vector includesgenerating the second test vector by simultaneously inverting thesignals at the change points at which the signals of the plurality ofextracted asynchronous transfer points of the calculated logic circuitoutput vary.
 16. The method according to claim 13, wherein thegenerating a second test vector includes generating the second testvector by inverting the signal of the asynchronous transfer point of thelogic circuit output, when the signal of the extracted asynchronoustransfer point of the calculated logic circuit output is a constantsignal.